Asynchronous Circuits Overview

Principles

Definition

Asynchronous circuits is the academic concept and research area concerned with the design, analysis, and implementation of digital logic circuits that do not rely on a global clock signal for synchronization. This field investigates principles for event-driven computation, focusing on local communication protocols, such as handshaking, to coordinate data flow and operations between circuit components. Key characteristics explored include the absence of clock skew issues, potential for dynamic power management based on workload, and performance determined by average-case data path delays rather than worst-case timing. Its significance lies in exploring alternatives to conventional synchronous design paradigms, offering potential advantages in power efficiency, speed variability, robustness to process variations, and electromagnetic interference reduction, while addressing complex challenges in formal verification and timing analysis.

Ontological type

Design Methodologies

Handshaking Protocols

Timing and Hazard Analysis

Key developments

Key Figures

Deterministic Robustness era

Kwabena Boahen[1], affiliated with Johns Hopkins University[3] and the University of Pennsylvania[4], is a key contributor in this era. His 2000 paper Point-to-point connectivity between neuromorphic chips using address events[7] introduced a pragmatic approach to interchip communication for neuromorphic systems, a contribution that advanced asynchronous interconnects and helped establish deterministic timing and hazard-mitigation considerations in clockless designs. Steven M. Burns[2], affiliated with University of Washington[5] and the California Institute of Technology[6], is another pivotal figure in this era. His 1989 paper The design of an asynchronous microprocessor[8] laid out foundational principles for asynchronous, clockless computation, underpinning verification methods and formal timing models that supported robust design in deterministic clockless circuits.

Desynchronization and Delay Tolerance era

John V. Arthur[1] is associated with Stanford University[3] and University of Pennsylvania[4] during the Desynchronization and Delay Tolerance era. His key contributions center on the TrueNorth project, notably TrueNorth: Design and Tool Flow of a 65 mW 1 Million Neuron Programmable Neurosynaptic Chip[5], which demonstrated a scalable, energy-efficient neuromorphic platform and catalyzed hardware-software co-design for robustness to variability. Paul Merolla[2] is affiliated with Stanford University[3] and University of Pennsylvania[4] during this era. His key contribution, as co-author of TrueNorth: Design and Tool Flow of a 65 mW 1 Million Neuron Programmable Neurosynaptic Chip[5], delivered a low-power, massively parallel substrate enabling robust operation under delay and process variation, accelerating scalable neuromorphic integration during this era.

Event-Driven Clockless era

Tingwen Huang [1] is a researcher active in the Event-Driven Clockless era, with affiliations at University of Wisconsin–Madison [3] and Sun Yat-sen University [4]. His key contribution in this era, as embodied by Event-Based Synchronization Control for Memristive Neural Networks With Time-Varying Delay [7], demonstrates how event-triggered synchronization enables stable, low-power operation of memristive networks under time-varying delays, aligning with the era's energy-aware asynchronous control. Shiping Wen [2] is a prominent figure in this era, with affiliations at Huazhong University of Science and Technology [5] and Tongji University [6]. His contributions, as reflected in the same Event-Based Synchronization Control for Memristive Neural Networks With Time-Varying Delay [7], illustrate how event-based synchronization for memristive systems supports robust, low-energy clockless operation across distributed platforms, underscoring the era's focus on practical, energy-aware primitives [7].